The present invention relates to the field of semiconductor memory devices, and in particular to a DRAM array having a compact folded bitline architecture.
It is a continuing goal in computer memory design, such as in the design of Dynamic Random Access Memory (DRAM) arrays, to achieve increased storage capacity in smaller devices. Typically, this entails finding ways of packing memory cells as densely as possible into as small an area as possible.
In DRAM arrays, individual memory cells are accessed by bitlines and wordlines. Generally speaking, one limitation on the degree to which the size of a memory cell in an array can be reduced is determined by the "pitch" of the bitlines and wordlines required to address a single cell. A pitch is equivalent to the width of a bitline or wordline, plus the distance to neighboring bitlines or wordlines in the array.
FIG. 9A shows a memory cell 900 in a DRAM array. The cell is accessed, for reading from or writing to, by a bitline 901 and a wordline 902. FIG. 9A illustrates, for example, that for a bitline pitch of 3F (where "F" is the minimum lithographic feature size and is technology-dependent) and a wordline pitch of 2F, the minimum size for a memory cell in the array is approximately 6F.sup.2. Similarly, as shown in FIG. 9B, for a bitline pitch of 2F and a wordline pitch of 2F, a memory cell 903 having an area of only 4F.sup.2 can be accessed.
Folded bitline architecture is known in DRAM arrays. In folded bitline architecture, the voltage on a selected bitline is compared to a voltage on a complement bitline. The complement bitline provides a reference signal for comparison to the signal on the selected bitline such that the actual stored bit in an array memory cell is distinguished as the difference between signals on the selected bitline and the complement bitline.
Conventionally, in a folded bitline DRAM, the bitlines of the memory array are laid out so that each bitline and its associated complement are parallel to each other on the same level. FIG. 9C shows an example of a memory cell accessed by a folded bitline architecture. In FIG. 9C, bitline 901 and its complement 901, and wordline 902 are used to access memory cell 904. The arrangement requires a minimum of about 8F.sup.2 semiconductor area per cell to implement.
Open bitline architectures are known which have a theoretical minimum of 4F.sup.2 array area per cell, but folded bitline architecture is preferable in that it provides better noise immunity.
Techniques have been disclosed for providing the advantages of folded bitline architecture while reducing the minimum cell area required. Nakano et. al (1996 Symposium on VLSI Circuits Digest of Technical Papers, p. 190-191) describes a bitline architecture in which a bitline and its complement are vertically parallel on subsequent levels rather than being adjacent and parallel on the same level. The lower bitline is connected to the underlying cells by contacts. The bitline and its complement exchange levels in "twist regions" at one or more locations in order to match capacitance. The architecture supports a minimum cell size of 5-6F.sup.2.
However, the twist region layout of Nakano et al. does not allow the array to continue uninterrupted through the twist region. Instead, a gap, i.e., an absence of memory cells, in the layout pattern exists which reduces the array density. The gap is necessitated by a crowding of contacts within the twist region, and by a third metal level which is used for the exchange of bitline levels. As this level is normally fully utilized within the array as the wordline, a gap in the array is required to allow its use within the twist region.
U.S. Pat. No. 5,821,592 to Hoenigschmid et al. describes a bitline architecture which eliminates the afore-mentioned gaps, to achieve an improvement in array density. The architecture supports a minimum cell size of approximately 6F.sup.2.